1. Field of the Invention
The present invention relates to a recess transistor (TR) gate in a semiconductor device. More particularly, the present invention relates to a recess transistor gate having increased space between adjacent recess gates and a method of forming the same.
2. Description of the Related Art
In order to achieve higher density, conventional dynamic random access memory (DRAM) cells utilize a storage capacitor and an insulated gate field effect transistor (FET). DRAM cells have been successively scaled down in size to the sub-micron range. However, as a result of this reduction in size, there are many challenges in designing a planar gate. As the width of the planar gate narrows accompanied with shorter channels, problems such as junction leakage, source/drain breakdown voltage, and data retention time become issues of concern. Efforts to increase the density and the required gate channel length have led to the development of a recess gate being formed within a silicon substrate. Conventionally, a width of a planar gate on an active region, i.e., an access gate, is larger than a width of a planar gate on a field region, i.e., a pass gate. The narrow space between the gates gives rise to a self-aligned contact (SAC) open margin problem.
FIG. 1 illustrates a plan view of a conventional DRAM cell gate layout according to the prior art.
In FIG. 1, a substrate (not shown) includes an active region 10 and a field region 18. A gate layer 12 is formed over the substrate to intersect the active region 10. An access gate 12a is formed over each intersection of the gate layer 12 and the active region 10. Reference character W1 represents a width of an access gate 12a. A pass gate 12b is formed over each intersection of the gate layer 12 and the field region 18. Reference character W2 represents a width of a pass gate 12b. 
A BC SAC region 14 is formed at a periphery of the active region 10. Reference character d1 represents a distance between an access gate and an adjacent pass gate, i.e., a size of the BC SAC region. A DC SAC region 16 is formed at a center of the active region 10. Reference character d2 represents a distance between adjacent access gates, i.e., a size of the DC SAC region. In this conventional arrangement, the width W1 of an access gate 12a is designed to be larger than the width W2 of a pass gate 12b. 
Thus, as may be seen in this conventional planar gate structure, the width W1 of the access gate 12a is larger than the width W2 of a pass gate 12b. Conventionally, it is necessary that the width W1 of the access gate 12a be larger than the width W2 of the pass gate 12b in order to increase the refresh time in the planar type gate. This arrangement, however, leads to the self-aligned contact (SAC) open margin problem as described above.